Smc-networks SMC91C95 Manual do Utilizador Página 102
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102
For example, if an odd pointer value is loaded,
first a byte is pre-fetched into the FIFO, and
immediately a full word is pre-fetched
completing three bytes into the FIFO. If the
CPU reads a word, one byte will be left again a
new word is pre-fetched.
In the case of write, if an odd pointer value is
loaded, and a full word is written, the FIFO
holds two bytes, the first of which is
immediately written into an odd memory
location. If by that time another byte or
word was written, there will be two or three
bytes in the FIFO and a full word can be written
into the now even memory address.
When a CSMA/CD cycle begins, the arbiter will
route the CSMA/CD DMA addresses to the
MMU as well as the packet number associated
with the operation in progress. In full-duplex
mode, receive and transmit requests are
alternated in such a way that the CPU
arbitration cycle time is not affected.
- SMC91C95 1
- TABLE OF CONTENTS 2
- Related Documentation 2
- 128 Pin VTQFP 3
- GENERAL DESCRIPTION 4
- OVERVIEW 4
- PIN REQUIREMENTS 7
- DESCRIPTION OF PIN FUNCTIONS 10
- FUNCTIONAL DESCRIPTION 21
- TX COMPLETION 26
- RESET LOGIC 33
- THEORY OF OPERATION 69
- “Magic Packet” Support 70
- FIGURE 12 - RX INTR 75
- FIGURE 13 - TX INTR 76
- FIGURE 14 - TXEMPTY INTR 77
- OPERATIONAL DESCRIPTION 104
- FIGURE 20 - I/O READ TIMING 110
- (Table on the following page) 110
- POWERDOWN 118
- FIGURE 36 - EEPROM READ 127
- FIGURE 37 - EEPROM WRITE 128
- FALLING RXCLK) 130
- GAGE PLANE 136
- 300 Kennedy Drive 138
- Hauppauge, NY 11788 138
- (516) 435-6000 138
- FAX (516) 231-6004 138
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