Smc-networks Sharp ARM720T_LH79520 Manual do Utilizador descarregar pdf (Página 1)

ARM720T_LH79520 – Sharp LH79520 SoC

with ARM720T 32-bit RISC Processor

Summary

Core Reference

CR0162 (v2.0) March 10, 2008

This document provides information on Altium Designer's Wishbone wrapper support

for the discrete Sharp Bluestreak® LH79520 – a fully integrated 32-bit System-on-

Chip (SoC), based on an ARM720T 32-bit RISC processor core.

Altium Designer's ARM720T_LH79520 component is a 32-bit Wishbone-compatible RISC

processor.

The ARM720T macrocell within the

physical LH79520 is built around an

ARM7TDMI-S core processor. This

processor is an implementation of the

ARM architecture v4T.

Although placed in an Altium Designer-based FPGA project just like any other 32-bit

processor component, the ARM720T_LH79520 is essentially a Wishbone-compliant wrapper

that allows communication with, and use of, the discrete ARM720T processor encapsulated

within the Sharp Bluestreak LH79520 device. You can think of the wrapper as being the

'means' by which to facilitate use of external memory and peripheral devices – defined within an FPGA – with the discrete

processor.

The ARM720T_LH79520 wrapper can be used in FPGA designs targeting any physical FPGA device – you are not constrained

to a particular vendor or platform.

Features

• 3-stage pipelined RISC processor

• 4GByte address space

• 32-bit ARM instruction set

• Wishbone I/O and memory ports for simplified peripheral connection

Code written for the ARM720T is

binary-compatible with other members

of the ARM7 family of processors. It is

also forward-compatible with ARM9,

ARM9E, and ARM10 processor

families.

• Full Viper-based software development tool chain – C compiler/assembler/source-level

debugger/profiler

• C-code compatible with other Altium Designer 8-bit and 32-bit Wishbone-compliant

processors, for easy design migration.

For further information on ARM720T features, refer to the following documents, available from

www.arm.com:

•

ARM720T Technical Reference Manual

•

ARM7TDMI-S Technical Reference Manual

For further information on LH79520 features, refer to the following documents, available from

www.sharpsma.com:

•

LH79520 Product Brief

•

LH79520 Data Sheet

•

LH79520 System-on-Chip User's Guide

Available Devices

From a schematic document, the ARM720T_LH79520 device can be found in the FPGA Processors integrated library (FPGA

Processors.IntLib

), located in the \Library\Fpga folder of the installation.

From an OpenBus System document, the ARM720T_LH79520 component can be found in the

Processor Wrappers region of

the

OpenBus Palette panel.

CR0162 (v2.0) March 10, 2008 1

1 2 3 4 5 6 ... 27 28

Resumo do Conteúdo

Página 1 - Summary

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Summary Core Reference CR0162 (v2.0) March 10, 2008 This document provides i

Página 2 - RISC Processor Background

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Memory & I/O Management The ARM720T_LH79520 uses 32-bit address buses provi

Página 3 - Wishbone Bus Interfaces

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 5. Memory devices mapped into banks 0- 4 (cs0-cs4) of the ARM720T_LH7

Página 4 - Design Migration

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor The adjacent flow chart shows the process that was followed to build this memor

Página 5 - Architectural Overview

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • cs0 (Bank 0) – 4000_0000h to 43FF_FFFFh • cs1 (Bank 1) – 4400_0000h to 47

Página 6 - Pin Description

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor The size of the RAM can vary between 1KB and 16MB, dependent on the availabilit

Página 7

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor clock signal (CLK_I), an acknowledge signal fails to appear from the addresse

Página 8 - Configuring the Processor

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • for an unsigned read, the processor will pad-out the remaining 24 or 16 bits

Página 9

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Hardware Description For detailed information about the hardware and function

Página 10 - Memory & I/O Management

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Wishbone Communications The following sections detail the standard handshaking

Página 11

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Reading from a Slave Wishbone Memory Device Data is read by the host processo

Página 12 - Division of Memory Space

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor RISC Processor Background RISC, or Reduced Instruction Set Computer, is a term

Página 13 - Internal Memory

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Placing an ARM720T_LH79520 in an FPGA design How the ARM720T_LH79520 is placed

Página 14 - Peripheral I/O

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Design Featuring an OpenBus System Figure 11 illustrates identical use of the

Página 15 - Data Organization

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 12. Wiring the OpenBus System-based ARM720T_LH79520 to the physical pin

Página 16

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor As the physical ARM720T processor does not reside within an FPGA, communicati

Página 17 - Hardware Description

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor • Download of the embedded code targeted to the discrete ARM720T device. Click

Página 18 - Wishbone Communications

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 16. Starting an embedded code debug session. The debug environment of

Página 19 - Wishbone Timing

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 17. Workspace panels offering code-specific information and controls F

Página 20 - CR0162 (v2.0) March 10, 2008

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Figure 19. Accessing debug features from the processor's instrument pan

Página 21

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Instruction Set The ARM7TDMI-S core processor – on which the ARM720T is based –

Página 22 - Facilitating Communications

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Improving and Extending Product Life-Cycles Fast time to market is usually sy

Página 23 - Downloading Your Design

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Wishbone OpenBUS Processor Wrappers To normalize access to hardware and periphe

Página 24 - On-Chip Debugging

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Architectural Overview Symbol Figure 1. Symbols used for the ARM720T_LH79520

Página 25

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Pin Description The following pin description is for the processor when used on

Página 26

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Name Type Polarity/Bus size Description Peripheral I/O Interface Signals IO_S

Página 27

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Name Type Polarity/Bus size Description PER_RESET I Low Reset signal from the L

Página 28 - Revision History

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor Speed-critical (or latency-sensitive) parts of an application should also be